英语新闻丨应对芯片技术“卡脖子”的创新之道

Moore's Law has been a cornerstone of the rapid advancement of digital technology over the past decades, although it is now confronting physical limits and diminishing economic returns.

过去几十年，摩尔定律一直是数字技术快速进步的基石，尽管如今它正面临物理极限和边际收益递减的挑战。

For an industry conditioned to equate progress with nanometers, the Tau Scaling Law disclosed by Huawei on Monday is a challenge to the organizing logic of the semiconductor ecosystem.

对于一个习惯于用纳米衡量进步的行业而言，华为5月25日公布的“τ scaling law”（陶缩放定律）无疑是对半导体生态系统运行逻辑的一次挑战。

Instead of continuing the increasingly expensive race to shrink transistors, Tau Scaling proposes that future chip performance gains can come from compressing the signal propagation time through architectural and timing innovations. Huawei has set a target of reaching a chip density equivalent to 1.4 nanometers by 2031.

陶缩放定律提出，摒弃代价日益高昂的晶体管微缩竞赛，转而通过架构与时序创新压缩信号传播时间，驱动未来芯片性能提升。华为已设定目标，到2031年实现相当于1.4纳米制程的芯片密度。

Washington's export restrictions have attempted to cut China off from advanced lithography equipment, leading-edge foundries and portions of the global event-driven architecture software stack. Such measures were designed to slow China's progress in advanced semiconductors.

美国的出口限制试图将中国排除在先进光刻设备、前沿代工厂以及部分全球事件驱动架构软件栈之外。这些措施旨在减缓中国在先进半导体领域的进步。

That is where Tau Scaling enters the picture. Instead of shrinking transistor dimensions from 3 nm to 2 nm and beyond, Huawei is extracting more performance from mature process nodes such as 5 nm and 7 nm by means of architectural optimization, timing compression, logic folding and system-level coordination.

这正是陶缩放定律发挥作用的地方。华为不再追求从3纳米到2纳米及更小尺寸的晶体管微缩，而是通过架构优化、时序压缩、逻辑折叠和系统级协调等手段，从5纳米、7纳米等成熟工艺节点中挖掘更多性能。

Much of the underlying research — including asynchronous computing concepts, wave pipelining, and timing optimization techniques — can be traced back decades. What Huawei has done, under conditions where the traditional scaling route became inaccessible, is to revisit those ideas, combine them, enhance them and industrialize them.

许多基础性研究，包括异步计算概念、波流水线技术和时序优化技术等都可以追溯到几十年前。华为所做的，是在传统微缩路径受阻的情况下，重新审视这些想法，将它们加以融合、改进并产业化。

In that sense, the emergence of Tau Scaling reflects a broader historical pattern in technology. Constraints often redirect innovation rather than stop it. So, if chip performance can be improved through architecture rather than lithography alone, then the balance of competition changes. The key question becomes not simply who owns the most advanced EUV machines, but who can design the most efficient systems using available manufacturing capabilities.

从这个意义上说，陶缩放定律揭示了技术发展的一条普遍规律：限制往往促使创新转向，而非将其扼杀。若芯片性能可借架构而非单纯依赖光刻技术提升，竞争的格局便将随之改变。关键问题不再是“谁拥有最先进的极紫外光刻机”，而是“谁能利用现有制造能力设计出最高效的系统”。

It would be premature, though, to declare that the arrival of Tau Scaling heralds the post-Moore era. Semiconductor history is filled with elegant concepts that struggled once they encountered manufacturing economics, ecosystem inertia, or commercial realities. Huawei's proposal faces several important ceilings.

不过，现在就说陶缩放定律预示后摩尔时代已经开启，未免为时过早。半导体发展史上不乏精妙构想，但一旦遭遇制造经济学、生态系统惯性或商业现实，便会步履维艰。华为的方案目前仍面临若干关键瓶颈。

Architecture cannot completely replace physics. Timing optimization can reduce inefficiencies, but signals still obey physical propagation limits. As chips become larger and workloads more complex, interconnect delays and synchronization overhead remain major bottlenecks.

架构终究无法替代物理规律。时序优化虽能减少低效，信号却始终受制于物理传播的极限。随着芯片尺寸不断增大、工作负载日趋复杂，互连延迟与同步开销仍是绕不开的主要瓶颈。

Logic folding and time-domain optimization introduce their own complexity penalties. The more aggressively a design compresses timing, the harder verification, debugging and manufacturing become. Commercialization will determine whether Tau Scaling becomes an industry framework. For Huawei's approach to become influential, other companies must adopt it, customers must validate it and developers must build around it. That process will take years, not conference announcements.

逻辑折叠与时域优化本身也需付出复杂性代价。设计越激进地压缩时序，验证、调试与制造的难度便越大。陶缩放定律能否成为行业框架，最终取决于商业化落地。华为的方案要产生影响力，必须获得其他公司的采纳、客户的验证以及开发者的生态共建。这需要数年之功，而非一场发布会所能成就。

Even so, the broader lesson already stands. The semiconductor industry is entering a phase where innovation no longer relies exclusively on brute-force scaling and trillion-dollar capital expenditures. Architectural intelligence, software-hardware codesign, advanced packaging and system optimization are becoming increasingly important.

即便如此，一个更宏观的启示已然显现：半导体行业正步入新阶段——创新不再单纯依赖蛮力微缩与万亿美元级的资本投入。架构智能、软硬件协同设计、先进封装与系统优化，正变得日益关键。

For China, that shift creates both an opportunity and a responsibility. The country still faces major gaps in lithography, materials, EDA tools and manufacturing equipment. But Tau Scaling demonstrates something equally important: when external pressure blocks one route, researchers will look for alternative routes and solutions can emerge through persistence, engineering discipline and targeted input.

对中国而言，这一转变既是机遇，也是责任。尽管在光刻、材料、EDA工具及制造设备上差距显著，但陶缩放定律揭示了一个重要道理：外部压力堵住一条路，科研人员就会开辟另一条路。凭借坚韧、工程严谨和精准投入，解决方案终将破土而出。

The semiconductor race is no longer just about making things smaller. Increasingly, it is about making systems smarter. The challenge now is for more Chinese companies and engineers to push beyond incremental imitation and focus on resolving genuine choke-point technologies with the tools they already possess.

半导体竞赛，已从单纯追求“更小”转向致力实现“更智能”。当务之急，是更多中国企业与工程师超越渐进式模仿，立足现有工具，攻克真正的“卡脖子”技术。

Moore's Law /mʊəz lɔː/摩尔定律

diminishing economic returns /dɪˈmɪnɪʃɪŋ ˌiːkəˈnɒmɪk rɪˈtɜːnz/边际收益递减

conditioned to /kənˈdɪʃənd tuː/习惯于

Tau Scaling Law /taʊ ˈskeɪlɪŋ lɔː/ τ缩放定律（陶缩放定律）

semiconductor ecosystem /ˌsemikənˈdʌktər ˈiːkəʊsɪstəm/半导体生态系统

shrink transistors /ʃrɪŋk trænˈzɪstəz/微缩晶体管

advanced lithography equipment /ədˈvɑːnst lɪˈθɒɡrəfi ɪˈkwɪpmənt/先进光刻设备

leading-edge foundries /ˈliːdɪŋ edʒ ˈfaʊndriz/前沿代工厂

event-driven architecture /ɪˈvent ˈdrɪvən ˈɑːkɪtektʃə/事件驱动架构

asynchronous computing /eɪˈsɪŋkrənəs kəmˈpjuːtɪŋ/异步计算

wave pipelining /weɪv ˈpaɪplaɪnɪŋ/波流水线

EUV machines /ˌiː juː ˈviː məˈʃiːnz/极紫外光刻机

post-Moore era /pəʊst mʊə ˈɪərə/后摩尔时代

manufacturing economics /ˌmænjʊˈfæktʃərɪŋ ˌiːkəˈnɒmɪks/制造经济学

ecosystem inertia /ˈiːkəʊsɪstəm ɪˈnɜːʃə/生态系统惯性

software-hardware codesign /ˈsɒftweə ˈhɑːdweə ˌkəʊdɪˈzaɪn/软硬件协同设计

advanced packaging /ədˈvɑːnst ˈpækɪdʒɪŋ/先进封装

system optimization /ˈsɪstəm ˌɒptɪmaɪˈzeɪʃən/系统优化

lithography /lɪˈθɒɡrəfi/光刻

EDA tools /ˌiː diː ˈeɪ tuːlz/电子设计自动化工具