Smarter Power Sequencing with GreenPAK

Power sequencing may not be the most visible part of a system design, but it plays a critical role in ensuring complex electronic systems start up reliably, recover from faults gracefully, and shut down safely. In this episode of the EE Times Podcast, host Erik Singer sits down with Dima Mymrikov, Senior Director of Product Marketing at Renesas Electronics, to discuss why power sequencing remains a fundamental challenge for embedded developers and how evolving design approaches are helping engineers build more robust systems.

IMChip’s founders say interface memristors are more reliable and scalable than filamentary ones. The Groningen spin-out grows the devices at high temperature, then transfers them onto silicon. In this month’s Brains and Machines, Sunny Bains talks with Tamalika Banerjee, chief scientific officer, and Ruben Hamming-Green, head of R&D, about their plan for an edge-AI prototype chip within two years. Giulia D’Angelo of the Czech Technical University in Prague and Ralph Etienne-Cummings of Johns Hopkins University join the discussion.

IMChip’s founders say interface memristors are more reliable and scalable than filamentary ones. The Groningen spin-out grows the devices at high temperature, then transfers them onto silicon. In this month’s Brains and Machines, Sunny Bains talks with Tamalika Banerjee, chief scientific officer, and Ruben Hamming-Green, head of R&D, about their plan for an edge-AI prototype chip within two years. Giulia D’Angelo of the Czech Technical University in Prague and Ralph Etienne-Cummings of Johns Hopkins University join the discussion.

As AI-driven SoCs move to advanced process nodes, design complexity, development cost, and execution risk are rising sharply. In this episode, Synopsys Executive Director of Product Management Ravi Todi explains why competitive power, performance, and area (PPA) are no longer sufficient on their own. Success in the AI era also depends on predictable execution and disciplined management of total cost of ownership (TCO) across the full SoC lifecycle.The discussion highlights how a holistic, silicon-proven Foundation IP platform—delivered as an integrated solution from a single trusted partner—can help reduce risk early, minimize integration issues and re-spins, accelerate yield ramp, and deliver differentiated PPA for high-performance compute AI, and edge AI designs. Ravi also explores how deep foundry alignment and EDA co-optimization reveal the true cost of fragmented IP sourcing beyond license price, enabling teams to meet demanding market requirements, achieve faster and more predictable tape-outs, and lower overall SoC TCO.

In this month's Brains and Machines, Dr. Ryad Benosman discusses event-based vision, retinal prosthetics, and neuromorphic startups with Dr. Sunny Bains of University College London. A co-founder of Prophesee, he explains why he believes AI's future must come from neuromorphic engineering. Discussion follows with Dr. Giulia D’Angelo from the Czech Technical University in Prague and Professor Ralph Etienne-Cummings of Johns Hopkins University. 

As systems become more software-defined, the traditional development model of waiting for hardware before serious software validation begins is no longer sustainable. Software teams need platforms earlier. Hardware teams need realistic workloads sooner. Verification teams need better ways to expose system-level issues before tapeout. We will look at how digital twins are becoming the shared foundation for this new HW/SW co-development model. Using virtual platforms, hardware emulation, and FPGA prototyping, teams can start earlier, collaborate more closely, and design/optimize/validate with greater confidence. We will also discuss new system-level verification challenges in power, performance, and DFT, showing how pre-silicon Hardware platforms can help teams find critical issues earlier and deliver more robust software-defined systems.

Artificial intelligence is accelerating semiconductor development, but more compute, more automation, and more engineering data do not automatically create better decisions. As design and manufacturing workflows become increasingly AI-enabled, a new constraint is emerging: trust. In this episode, Dr. Jim Shiely builds on themes from his Patterning the Singularity leadership work to explore the semiconductor industry’s “trust bottleneck” and why trustworthy engineering intelligence is becoming essential to future innovation.

On this month's episode of Brains and Machines, five engineers debate neuromorphic sensing and learning. Recorded at the Neuromorphic Hardware and Algorithms conference at the University of Sussex, the panel explores whether events and spikes are the right framework for integrating sensor modalities, motor control, and learning across systems. They also examine commercial directions and revisit the perennial question: what is neuromorphic engineering?The panelists are:Dr. Chiara Bartolozzi (Italian Institute of Technology) Dr. Federico Corradi (Eindhoven University of Technology) Dr. James Knight (University of Sussex) Dr. Laura Kriener (Institute of Neuroinformatics, Zurich) Dr. Sebastian Siegel (Peter Grünberg Institute, Jülich)The session is chaired by Dr. Sunny Bains (University College London), followed by a discussion with Dr. Giulia D’Angelo (Czech Technical University in Prague) and Professor Ralph Etienne-Cummings (Johns Hopkins University).

For years, AI infrastructure was measured at the scale of the data center. That's changed. In this episode, Neeraj Paliwal explains why the rack has become the indivisible unit of a modern AI system — designed as one system rather than a collection of servers — and why performance is no longer defined by the compute in any single box, but by how efficiently data moves, is stored, and is secured across the entire rack. And getting there depends on co-designing the silicon, memory, interconnect, and packaging together, with the IP foundation turning concentrated power into usable compute.

As AI agents grow more capable, the question of trust becomes increasingly critical, especially in complex engineering environments like semiconductor and PCB design. Siemens EDA and NVIDIA are tackling that challenge head-on, combining deep EDA domain expertise with cutting-edge AI infrastructure to deliver a new generation of agentic AI capabilities for engineering teams. In this episode, we sit down with Amit Gupta, Chief AI Strategy Officer at Siemens EDA, and Tim Costa, VP and GM of Industrial and Computational Engineering at NVIDIA, to explore how their collaboration is shaping the future of EDA workflows. Together, they discuss domain-scoped AI agents that don't just execute tasks but verify their own outputs using physics-based EDA software validation, purpose-built to support the demands of long-running engineering workflows. We dig into what self-verifying agentic AI actually means in practice, what the Siemens and NVIDIA collaboration looks like under the hood, and what it delivers in terms of tool-calling reliability, token efficiency, result quality, and time-to-results for engineering teams working across the full EDA lifecycle.