Semi Doped

The fundamental physics of data movement are forcing a shift to new memory architectures for AI inference. Sudeep Bhoja, co-founder and CTO of d-Matrix, joins Vik to detail the company's journey from a non-consensus bet on memory-bound inference to a full-rack 3D-stacked DRAM solution. Sudeep explains the pivot from analog to digital in-memory compute, the system-level disaggregation strategies for their Corsair card, and how the next-generation Raptor chip integrates with Nvidia's ecosystem."Essentially, we got 16 times the capacity of SRAM, while we retained SRAM bandwidth."— Sudeep Bhoja, d-MatrixPresented by Crusoe: Fine-tune and serve open models without managing a single GPU. When we sat down with Crusoe’s product team, Austin asked: what will you do with my data? Their answer: They don’t touch or see it. Your training data is encrypted so even Crusoe’s own admins can’t see it, and the fine-tuned model is yours. Deploy on Crusoe in one click, or download and run it anywhere. Upload a dataset, pick an open model, and pay per token rather than per GPU hour. Run a few versions, compare them, and download the one that works best. Accounts are free, and get $5 in credit when you sign up. Try Serverless Fine-Tuning: https://semidoped.com/crusoeKey Takeaways:- The core problem in AI inference is a 1000x energy gap. Compute costs femtojoules per operation, but moving data from memory costs picojoules per bit.- d-Matrix's first analog in-memory compute chip failed because it couldn't maintain 32-bit accumulation precision, forcing a pivot to a digital architecture.- The Corsair card's digital in-memory compute delivers 150 TB/s of on-chip SRAM bandwidth — over 8x more than an Nvidia Blackwell GPU's 18 TB/s HBM.- The next-gen Raptor chip stacks a logic die on a DRAM die, delivering 16x the capacity (32 GB) of the prior SRAM design while retaining ~100 TB/s bandwidth.- This 3D stacking is over 10x more energy-efficient than HBM4, consuming just 0.37 pJ/bit versus an estimated 5 pJ/bit for an HBM4-plus-GPU system.- Choosing the stacking order is a 'pick your poison' trade-off. d-Matrix put logic-on-top for better thermals, accepting a harder power delivery challenge through the DRAM.- The go-to-market product is a full rack with 144 Raptor packages, aggregating 2.3 TB of high-bandwidth memory designed to drop into Nvidia's VR rack infrastructure.This episode is supported by Meter. You have the GPUs and the power. Now who builds the network, and who do you call when it breaks? Meter designs, deploys, and runs frontend, storage, and management networks on its own switches and its own network OS. One call reaches the team that designed the hardware and wrote the software. https://semidoped.com/meterChapters:0:00 Intro: The Cost of a Token3:28 The 2019 Bet on Inference7:43 Nighthawk: Analog In-Memory Compute12:08 Why Analog Failed19:02 Corsair: Digital In-Memory Compute26:04 System Strategy: Speculative Decoding37:05 Raptor: 3D Stacked DRAM39:40 The 'Free Lunch' of 3D Stacking45:00 Trade-off: Logic-on-Top vs DRAM-on-Top54:14 Go-to-Market: The Nvidia VR Rack1:03:17 The Future: Lightning & 4-High Stacks1:12:45 The End State of InferenceFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Marvell's potential acquisition of Lumentum is a strategic vertical integration play to capture the massive value optical components now unlock in the AI era. Andrew Schmitt and Scott Wilkinson of market research firm Signal AI join Austin and Vik to break down the deal's core drivers. They explain how Marvell could run the 'Broadcom playbook' by bundling DSPs and optics, even at the cost of competing with its own customers, and why Lumentum's future-facing assets like Optical Circuit Switches (OCS) and high-power lasers are just as critical as its current-gen transceivers.This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoeKey Takeaways:- The deal's driver is vertical integration, not securing laser capacity. Marvell wants to control the supply chain from chips to optics to co-design superior products for the fast-moving AI market.- The economics have flipped. Optics margins have doubled from ~25% to nearly 50%, making them attractive for chipmakers to acquire — even if it means Marvell pays 20-30x what it might have cost years ago.- Lumentum's real moat is manufacturing scale. While others can build a hundred 'unicorn' devices like 200G EMLs, Lumentum's advantage is its ability to produce them reliably by the million.- The acquisition creates channel conflict. Marvell's DSP customers will now have to compete with a vertically integrated Marvell-Lumentum, a dynamic that has already pushed some players out of the coherent market.- This is also a bet on future architectures. The deal secures Lumentum's critical assets for next-gen data centers, including Optical Circuit Switches (OCS) and high-power lasers for CPO and NPO.- Lumentum has the capacity to do both. After a 4x expansion of its Indium Phosphide fab, it can supply a vertically integrated Marvell and continue selling lasers to the open market.- A bidding war is likely. The guests speculate the news leak was intentional to attract other suitors like Nvidia, who could run the same vertical integration playbook.Chapters:0:00 Intro: Marvell & Lumentum7:38 The Vertical Integration Driver9:17 The Channel Conflict Problem14:58 Transceiver Value Chain17:38 Why Would Lumentum Sell?21:23 Lumentum's InP Capacity24:52 The Cost of Waiting27:00 Manufacturing Scale Is the Moat31:30 How AI Changed Component Value33:43 CPO: The Integration Endgame36:50 The 'Broadcom Playbook'38:58 Prediction: A Bidding WarFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/Chapters:0:00 Intro: Marvell & Lumentum7:38 The Vertical Integration Driver9:17 The Channel Conflict Problem14:58 Transceiver Value Chain17:38 Why Would Lumentum Sell?21:23 Lumentum's InP Capacity24:52 The Cost of Waiting27:00 Manufacturing Scale Is the Moat31:30 How AI Changed Component Value33:43 CPO: The Integration Endgame36:50 The 'Broadcom Playbook'38:58 Prediction: A Bidding WarFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Intel's EMIB technology represents a scalable, cost-effective advanced packaging solution that now serves as a core strategic differentiator for its foundry services. Ravi Mahajan, a distinguished engineer at Intel Foundry, joins Austin to detail EMIB's 20-year journey from a "science fiction" concept to a high-volume manufacturing reality. They discuss the principle behind EMIB, interconnect where you need it and only where you need it: small silicon bridges carry the fine-pitch die-to-die signals, while the organic substrate's thick metal still delivers power and everything else. They also cover its manufacturing advantages over CoWoS and Intel's forward-looking roadmap for active bridges and top-side optics.This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe"When first envisioned, this was almost science fiction because the bridge I was talking about is roughly half the thickness of an A4 sheet of paper. So imagine being able to manipulate tiny strips of silicon like that."— Ravi Mahajan, Intel FoundryKey Takeaways:- EMIB was invented to outpace organic packages, whose wire escape density at the die edge improved only about 10% per generation. The principle Ravi keeps returning to is interconnect where you need it and only where you need it: fine-pitch silicon in small local patches at the die edges, with the organic substrate's thick metal still carrying power and everything else. Fine wires are a poor way to deliver power anyway, and small bridges cut from a wafer keep the silicon cost down.- Bringing EMIB from concept to production required the convergence of five distinct technologies, including a custom 4-layer silicon process and handling dies half the thickness of an A4 sheet of paper.- Intel strategically chose HBM as EMIB's first driver, betting that if it could solve for the highest-performance memory interconnect, the technology could then "waterfall down" to all other less demanding applications.- EMIB's advantage over CoWoS is manufacturing scale. Silicon only where you need it means small bridges instead of a full-sized silicon interposer, avoiding its high cost and poor wafer utilization, which is critical for large, multi-reticle AI packages.- The EMIB portfolio was planned from the start. The original patent included EMIB-T, which uses TSVs to solve the "torturous" power delivery path of routing power around the bridge instead of through it.- EMIB is an Intel Foundry exclusive. Packaging dies from other foundries is logistically straightforward, positioning advanced packaging as a key strategic differentiator for Intel's services.- Intel's future roadmap includes top-side optics, using the top surface of the package for optical I/O to complement the electrical I/O on the bottom, dramatically increasing total package bandwidth.Chapters:0:00 Intro: Ravi Mahajan1:44 Pathfinding & The HIR Roadmap7:58 The Two Drivers of EMIB15:15 Decoupling I/O and Power16:27 The 'Science Fiction' of EMIB20:36 HBM as the Killer App25:06 EMIB vs. CoWoS31:44 Chiplets, UCIe, and Packaging Tiers34:08 The EMIB Portfolio: T, M, Active37:01 An Intel Foundry Exclusive41:21 AI's Role in Packaging43:26 Future: Top-Side OpticsMentioned in this episode:- NEW EPISODE: Synopsys’s Amazon Deal and GPT-Synopsys: Ravi Subramanian (Semi Doped episode): https://daily.semidoped.com/p/new-episode-synopsys-will-take-aFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

A novel third option is emerging for data center interconnects between short-reach copper and power-hungry optics. Point2 CEO Sean Park joins Vik Sekar to explain his company's Active RF Cable (ARC) technology, which sends high-frequency radio signals over a flexible plastic waveguide. Park details how this approach targets the critical 5-10 meter "scale-up" problem for AI clusters, claiming significant advantages in cable density, power efficiency, and latency over existing solutions.This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoe"The bandwidth limitation simply comes from the existence of electrons. And this plastic, it doesn't have electron. So, in terms of bandwidth, it is unlimited. Bandwidth is unlimited. So, once our silicon works, we don't have to really change the this cable at all. Just scale the silicon, then it will it will be used for higher data rate."— Sean Park, Point2 TechnologyKey Takeaways:- The interconnect choice is no longer just copper vs. optics. Point2's Active RF Cable (ARC) creates a third category, sending 100-200 GHz signals over a plastic waveguide for the 5-10 meter reach AI scale-up requires.- The core density advantage is 4x over copper. ARC uses a single plastic core instead of a differential pair (2x gain), then sends two channels per core using frequency division multiplexing (another 2x gain).- The power savings come from silicon simplicity. By avoiding the laser, DSP, and TIA of optical modules, a 1.6T ARC module consumes <10 watts (~5 pJ/bit), with a roadmap to <2 pJ/bit for co-packaged versions.- The latency improvement is three orders of magnitude. Because it requires no DSP, ARC latency is in the sub-nanosecond range — 1,000x better than DSP-based optical solutions, which is critical for all-reduce operations.- The cable itself has a clear scaling path that copper lacks. A plastic waveguide is a dielectric with theoretically unlimited bandwidth, free of the skin effect that limits copper. Future speed gains will come from silicon shrinks alone.- Practicality in the rack is a key feature. The flexible plastic cable has a 4.7 mm bend radius, tight enough to wrap around a finger, making it easier to route in dense chassis than fragile optical fiber.Chapters:0:00 Intro: RF Over Plastic3:06 The Third Option8:27 Investor Validation13:20 How E-Tube Works15:16 The 4x Density Advantage18:28 Inside the OSFP Module29:51 4.7mm Bend Radius34:20 Roadmap to Co-Packaging36:09 The No-Gearbox Advantage42:00 Biggest Challenges49:57 The Physics of Scaling51:00 Origin Story: Wallpaper TVMentioned in this episode:- Plastic Cables for AI Clusters: Can Point2’s E-Tube Disrupt Copper and Optics? (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/plastic-cables-for-ai-clusters-etubeFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Austin Lyons and Vik Sekar host a micro-explainer on the two competing micro-emitter technologies for AI interconnects: microLEDs and microVCSELs. They break down Credo's surprising pivot at OCP from its microLED acquisition to a microVCSEL product, revealing the core physics that give microVCSELs superior speed and reach. The episode establishes the technical reasons why the industry is converging on microVCSELs for the critical 5-50 meter gap in AI data centers.This episode is presented by Crusoe. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoeKey Takeaways:- The new battleground for AI interconnects is the 5-50 meter "reach gap"—too long for copper cables limited to ~7 meters, but too short for expensive, supply-constrained InP long-reach optics.- MicroLEDs are limited by physics to ~3-5 Gbps over 5 meters. Their broad light spectrum causes "chromatic dispersion," smearing the signal and creating a hard ceiling on speed and reach.- To achieve high bandwidth, microLEDs require massive parallelism—bundling ~300 slow lanes to hit 1 Tbps—which introduces significant manufacturing complexity in coupling hundreds of fibers.- MicroVCSELs solve this, hitting 50 Gbps+ over 50 meters. Their "stimulated emission" physics creates a narrow, focused beam that suffers less from dispersion, enabling 10x the speed and reach of microLEDs.- The supply chain is a key advantage. MicroVCSELs use a mature Gallium Arsenide (GaAs) process on 8-inch wafers, shared with cell phones, giving them a cost and scale advantage over exotic InP optics.- MicroLEDs' niche is extreme heat. Their Gallium Nitride (GaN) material is highly temperature-insensitive, making them a candidate for very short-reach, high-reliability optics inside a hot server tray.Chapters:0:00 The Credo Pivot3:49 The Talk of OCP8:13 The 5-50 Meter Reach Gap12:52 How MicroLEDs Work21:10 MicroLEDs' Parallelism Problem22:55 How MicroVCSELs Work26:57 MicroVCSEL Performance Specs31:51 The Physics of VCSELs33:35 The Market Chooses MicroVCSELs35:45 MicroLEDs' Niche: Heat38:16 Teasing Future InterviewsMentioned in this episode:- PicoJool’s Al Yuen: The Case for GaAs VCSELs in Scale-Up Interconnects (Semi Doped episode): https://daily.semidoped.com/p/picojools-al-yuen-the-case-for-gaas- A MicroLED Field Trip to Avicena (Vik's Newsletter, paid): https://www.viksnewsletter.com/p/a-microled-field-trip-to-avicena- MicroLEDs vs. Lasers: The Linewidth Tradeoff (Vik's Newsletter, free): https://www.viksnewsletter.com/p/microleds-vs-lasers-the-linewidth-tradeoff- Understanding Energy Bands in Semiconductors (Vik's Newsletter, free): https://www.viksnewsletter.com/p/energy-bands-in-semiconductorsFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Microsoft's Maia 300 is a fully co-designed system, optimized to solve the memory-bound "data movement problem" of emerging agentic AI workloads. Saurabh Dighe, Corporate VP of Azure Hardware Systems at Microsoft, sits down with Austin to detail the architecture, from its TSMC N2P chiplet design enabling 18 TB/s of HBM4 memory bandwidth to its use of AI agents for automated kernel optimization. They discuss how this full-stack approach aims to maximize intelligence per watt and per dollar for Microsoft's planet-scale services.This episode is presented by @CrusoeAI. Crusoe's Serverless Fine-Tuning trains an open model like Llama, DeepSeek, or GLM on your own data, and you pay per million tokens, not per GPU hour. About $2 buys roughly 5M training tokens on smaller models. Get $5 in credit to start: https://semidoped.com/crusoeKey Takeaways:- Microsoft views AI inference as a data movement problem, not a compute problem. The energy cost of moving data to feed the compute engine can be two orders of magnitude higher than the compute itself.- The design of Maia 300 is driven by the shift from chat to agentic AI, which creates memory-bound workloads. The system delivers a 7x token throughput increase per rack over Maia 200, with a 5x increase in rack-level memory bandwidth.- Maia 300 uses a chiplet architecture to "extend the shoreline" of its single TSMC N2P compute die. This allows it to accommodate eight HBM4 stacks, delivering 18 TB/s of memory bandwidth.- Microsoft is using AI agents for "agentic kernel optimization" to automate the creation of low-level software. This strategy aims to bypass the manual optimization bottleneck and enable "Day-zero model availability" for new AI models.- The system is built for deployment flexibility. While servers use direct liquid cooling, a rack-level "heat exchanger unit" allows the 167 kW racks to be deployed in traditional air-cooled data centers.- The network is a two-tiered scale-up fabric built on standard Ethernet. Copper connects the 96 accelerators within a rack, while optics connect racks into superpods of up to 12,288 accelerators.Chapters:0:00 Intro: Saurabh Dighe1:39 Microsoft's Silicon Philosophy5:52 Workload Shift: Agentic AI9:32 The Data Movement Problem14:20 Crusoe Ad Read17:47 Maia 300 Specs24:07 Chiplets & HBM429:12 Prefill/Decode Disaggregation30:33 Two-Tiered Network35:45 NPO vs. CPO36:46 Rack-Scale Power & Cooling41:35 Agentic Kernel Optimization49:08 What's Next: Maia 400Follow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

The demand for workload-specific hardware is forcing a strategic shift in the semiconductor IP business. Synopsys's Ravi Subramanian joins Austin to discuss why the company is moving to a new royalty-based model for its custom "application optimized IP," starting with a billion-dollar deal with Amazon. Ravi also unpacks Synopsys's partnership with OpenAI and its vision for AI "agent engineers" that augment human designers, while explaining why physics-based simulation remains the ultimate ground truth.This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe"in physics we trust is because at the end of the day, the ground truth to have the confidence, not hallucinate and be deterministic in your outcome is really what defines is a product going to be successful or not."— Ravi Subramanian, SynopsysKey Takeaways:- The hyperscaler IP model is shifting. Because 1-2 applications drive most revenue, companies like Amazon now demand custom “application optimized IP” instead of standards-based IP.- Synopsys is adopting a new business model for this custom work: a license fee, a “customization fee” to prioritize scarce engineers, and for the first time, a royalty on the final chip.- This new royalty model mirrors the Arm-Amazon partnership from a decade ago, aligning Synopsys with its customer’s 12-month design cycles and expanding its role to system-level bring-up.- Synopsys’s AI strategy isn't just tools, but a new consumption model: customers can “hire” an AI agent engineer with a specific skillset, fitting directly into existing budgets and team structures.- The GPT-Synopsys partnership with OpenAI is a turnkey service bundling a specialized LLM, the necessary compute, and forward-deployed engineers to solve the key adoption hurdles of model quality and compute scarcity.- AI is for exploration, but physics is for verification. Accurately modeling a modern CFET requires 200x more device equations than a planar FET, a complexity that demands physics-based simulators as the ground truth.Chapters:0:00 Intro: The Amazon & OpenAI Deals2:39 Application Optimized IP6:04 The New Royalty Business Model12:14 How Standard IP Differentiates18:20 The Arm-Amazon Analogy22:00 Synopsys's Role in Test Chips26:06 The Three Stages of Chip Design31:27 The 'Agent Engineer' AI Model36:20 The GPT-Synopsys Partnership39:27 In AI We Believe, In Physics We TrustFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

The push to run AI agents on edge devices will not be driven by model labs or hardware vendors, but by service providers like Meta whose ad-based business models create a powerful financial incentive to offload massive cloud compute costs onto the user's own powerful-but-idle hardware. Austin Lyons and Vik Sekar break down why the failed "AI PC" push has given way to a new, economically-driven strategy for on-device AI. They discuss how Qualcomm's acquisition of Modular provides the key software layer and why the ultimate vision is an "ecosystem of you" where the device acts as a context-aware orchestrator between local and cloud compute.This episode is presented by Crusoe. Try Crusoe's managed inference for open models with $5 in free credits: https://semidoped.com/crusoe"[Model Labs] business model is we make money when we do inference in the cloud. And yet we are saying, actually, there's a world where we would really like to just run this stuff locally... Meta's like, bro, I want to help you at the edge."— Austin Lyons, ChipstratKey Takeaways:- The driver for edge AI is a business model conflict. Model labs like OpenAI sell cloud inference; service providers like Meta see it as a massive cost center for their ad-supported agents like Muse.- Your phone is an underutilized edge server. Its specs—like 8GB of RAM and 2 vCPUs of power—are comparable to the dedicated cloud VMs that services like Meta's Muse provision for each user.- The "AIPC" push failed because it was a hardware-first strategy without a use case. Today's edge AI push is a software-first strategy driven by the need to cut cloud OpEx for mass-market agents.- The role of the edge device is becoming a "context translation layer." It uses private data like location and biometrics to intelligently decide which AI tasks run locally versus in the cloud.- Qualcomm's acquisition of Modular is a key strategic move. It positions the open-source Mojo language as the "write once, run anywhere" software layer for deploying agents across diverse hardware.- Personal agents will lead to the "end of apps." Fixed UIs, which force a designer's paradigm on the user, will be replaced by interfaces generated on demand via natural language.- Google is missing its opportunity to lead in on-device AI. Despite vertical integration from TPUs to Pixel hardware and a leading ad business, it lacks the product execution of players like Meta.Chapters:0:00 Who Makes Local AI Happen?1:25 Making the Intro with AI4:43 Qualcomm's Agent Vision6:54 Why AIPCs Failed8:45 The Phone as a Portal13:52 Meta's Incentive for Edge AI24:05 The End of Apps & UIs?32:31 The Ideal Personal Agent34:25 The Edge as a Context Layer38:17 Qualcomm's Modular Acquisition43:16 The Ecosystem of You48:01 Google's Missed OpportunityFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

As embedded flash hits a physical and economic scaling wall below 22nm, a new on-chip memory is needed. Ilan Sever of WeeBit Nano joins to explain how Resistive RAM (ReRAM) is positioned to become the new standard by offering a low-cost, high-endurance alternative. Ilan details how ReRAM's simple back-end-of-line integration, automotive qualification, and future applications in AI in-memory compute create a compelling replacement for the incumbent technology."In geometries below 28 or 22 nanometer, flash reached its physical limit, actually. So physically you cannot implement embedded flash anymore and the industry had been looking for alternative technologies for a few decades now."— Ilan Sever, WeeBit NanoKey Takeaways:- The inflection point for on-chip memory is physical. Embedded flash cannot scale below the 28/22nm node because its floating gate becomes too small to reliably hold charge.- The economic problem with eFlash is its 25-30% cost increase, a result of adding 8-10 extra masks to a standard CMOS process—a non-starter for cost-sensitive MCUs.- ReRAM's manufacturing advantage is its simplicity. It's built in the back-end-of-line (BEOL) metal layers, adding only two masks and not interfering with the sensitive transistors below.- The physics are different: ReRAM isn't storing charge, it's changing resistance by using voltage to form or dissolve a conductive filament of oxygen vacancies in a dielectric.- Automotive qualification is the key market validation. WeeBit's ReRAM is qualified for the AEC-Q100 standard and demonstrates 100,000 write cycles—10x that of typical eFlash.- The business model isn't just a recipe; it's a full IP module with the bit cell, analog circuits, digital logic, and programming algorithms, which is what SoC designers actually need.- Beyond replacing flash, ReRAM (as a memristor) is a foundational technology for future in-memory compute (IMC) AI accelerators that perform calculations inside the memory to save power.Chapters:0:00 The Overlooked Memory4:15 The eFlash Scaling Wall6:03 Four Uses of NVM23:19 The Cost of eFlash27:29 Introducing ReRAM32:25 How ReRAM Works37:12 Fab-Friendly Materials42:14 Automotive Qualification44:30 The Vertically Integrated IP Model51:13 Future: In-Memory Compute54:19 Innovation Story: Self-TrimmingFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/

Qualcomm re-entered the data center inference market late — competitive GPUs, XPUs, and custom accelerators are already out there. Durga Malladi (EVP/GM, Technology Planning, Edge & Data Center) explains why they didn't build another me-too accelerator and instead placed a differentiating technical bet: High Bandwidth Compute (HBC).The difference between HBC and HBM: HBM is stacked DRAM that shuttles data across wide buses to a separate accelerator — very high bandwidth, but expensive and power-hungry. HBC bonds stacked DRAM directly on top of a custom logic die using wafer-on-wafer techniques, so a lot of the compute runs literally next to memory. The result is lower latency and lower power per bit — and 18x effective bandwidth on the AI 250 versus the AI 200 at the SAME 768 GB LPDDR capacity and the SAME 160 kW per rack.Why the late-mover bet works: Qualcomm's differentiation isn't just architectural. Their foundry and memory-vendor relationships let them credibly promise the multi-megawatt-to-gigawatt supply hyperscalers need. Memory vendors are developing their own HBC-equivalent variants as partners rather than pure competitors, and Qualcomm expects the two technologies to co-evolve. Silicon is back in the lab; proof points land in Q1/Q2 2027.Chapters:0:00 Introduction2:49 The Memory Wall Problem8:05 HBC Physical Architecture9:33 HBC vs. Custom HBM11:50 Silicon Proof Points Coming12:08 Managing Thermals13:34 Dragonfly AI 25014:48 Trillion-Parameter Model on One Card16:56 Tokenomics and TCO18:26 Why TCO is Key19:26 Manufacturing at ScaleFollow Chipstrat:Newsletter: https://www.chipstrat.comX: https://x.com/chipstratFollow Vik:Newsletter: https://www.viksnewsletter.com/X: https://x.com/vikramskrFollow Semi Doped:Get more of Austin and Vik daily, free: https://daily.semidoped.com/